Real-Time FPGA Image Processing at 100 FPS
Real-time image processing in the FPGA: 100 FPS, deterministic latency, results feed directly into the control loop. Multi-stage evaluation using classical image-processing algorithms.
- 01
Starting Point
Image analysis supplies the actual value for a control loop, which imposes hard real-time requirements: 100 frames per second with guaranteed, constant latency from sensor to result. CPU and GPU solutions were ruled out, since jitter from scheduling and memory transfers is not tolerable inside a control loop.
- 02
Solution
We implemented the entire processing chain as a streaming pipeline in the FPGA: sensor interfacing, preprocessing, and multi-stage evaluation using classical image-processing algorithms. Each stage operates cycle-accurately on the pixel stream, with no buffering of entire frames. The result is available immediately after the frame ends and goes straight to the control loop, verified against a bit-exact reference model.
- 03
Result
100 FPS in continuous operation, deterministic latency under one millisecond, no dropped frames. The modular pipeline is reusable for new algorithms and sensors.